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Here's Some DDR5-4800: Hands-On First Look at Next Gen DRAM

by Anton Shilov on January 13, 2020 5:00 PM EST
  • Posted in
  • Memory
  • Trade Shows
  • DRAM
  • SK Hynix
  • DDR5
  • CES 2020
38 Comments | Add A Comment
38 Comments

Just like all major makers of DRAM, SK Hynix produced its first DDR5 memory chips a couple of years ago and has been experimenting with the technology since then. To that end, it is not surprising that the company displayed its DDR5 RDIMM at CES 2020, which implies that development is proceeding as planned.

At the trade show, SK Hynix demonstrated its 64 GB DDR5 RDIMM with ECC rated for a 4800 MT/sec/pin data transfer rate. The module marked as HMCA8GR8MJR4C-EB carries 20 memory chips marked as H5CNAG4NMJ as well as IDT’s P8900-Z2 register clock driver (RCD). The memory devices are marked differently than the ones SK Hynix used for 16 GB RDIMM back in late 2018, though we do not know the difference.

The DDR5 RDIMMS feature 288 pins on a slightly curved edge connector (to reduce the insertion force on every pin), just like DDR4 modules, yet its layout and design are a bit different when compared to DDR4 to prevent installment of DDR5 modules into DDR4 slots and vice versa.

It is unknown whether SK Hynix has already started to sample its DDR5 RDIMMs with developers of server platforms and servers, but it is obvious that all DRAM makers are aligning their DDR5 production schedules with CPU designers and other companies.

At present, it is unclear when exactly the first DDR5 platforms are set to hit the market, but a good guess would be 2021. One of the first platforms to confirm support for DDR5 memory has been Intel's Xeon Sapphire Rapids, set for deployment in the Aurora Supercomputer. AMD support for DDR5 is unknown so far.

Related Reading:

  • CES 2020: Micron Begins to Sample DDR5 RDIMMs with Server Partners
  • SK Hynix Details DDR5-6400
  • SK Hynix Develops First 16 Gb DDR5-5200 Memory Chip, Demos DDR5 RDIMM
  • Cadence & Micron DDR5 Update: 16 Gb Chips on Track for 2019
  • Cadence and Micron Demo DDR5-4400 IMC and Memory, Due in 2019
  • JEDEC: DDR5 to Double Bandwidth Over DDR4, NVDIMM-P Specification Due Next Year

Source: SK Hynix

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  • fred666 - Monday, January 13, 2020 - link

    why do they put the hole so close to the middle of the connector? It makes it uselessly hard to figure out the right way to insert the module on the motherboard
  • nandnandnand - Monday, January 13, 2020 - link

    So that an additional pin is physically closer to memory banks?
  • nierd - Monday, January 13, 2020 - link

    You mean the alignment notch? The physical thing that keeps you from being able to install a ddr2 dimm into a ddr5 slot? The one that ensures you put the memory in the correct way and not backwards?

    That's a pretty useful feature.
  • III-V - Monday, January 13, 2020 - link

    He's asking why so close to the middle, instead of closer to an edge.
  • tipoo - Monday, January 13, 2020 - link

    They're not asking why it exists, but why it's so close to the middle that it's not immediately obvious which side is which.
  • Tomatotech - Tuesday, January 14, 2020 - link

    If there was a notch at one of the bottom corners, that would help too. Realistically, almost nobody changes out RAM now, and the only people who do so, like you and me, are people who do it multiple times, so we will learn how to tell which way round it goes. There’s a blank area on one side of the central notch, so use thy to judge which way round it is.
  • sarafino - Monday, January 20, 2020 - link

    Two years ago a friend asked me to take a look at his first PC build to help him figure out why it wasn't working. He somehow managed to brute force his DIMM's in backwards.
  • Gastec - Saturday, February 8, 2020 - link

    I hope he is not driving, mistaking the brake and the acceleration pedals.
  • Gastec - Saturday, February 8, 2020 - link

    "They" :) Their majesties? Apaches?
  • CheapSushi - Monday, January 13, 2020 - link

    I think I know why. DDR5 can read AND write at the same time unlike DDR3 and DDR4 (they had to read, wait, write, wait). So both sides can work "independently" in a way. So the notch is splitting it more evenly because it's like two kits in one. There's much more to DDR5 than just a MHz and capacity bump.
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